AES协处理器IP核的设计与实现

Design and Implementation of AES Crypto Coprocessor IP Core

用Verilog语言设计了一种AES加密解密协处理器,并利用Xilinx公司的ISE8．2i软件和Spartan-3系列的FPGA对其进行验证和优化。本设计使用了少量的资源达到了比较高的数据吞吐量,形成可重用的AES加密解密协处理器的IP核。

An AES Crypto Coprocessor is designed with Verilog, validated and optimized using Spartan - 3 family FPGA and ISE8. 2i software by Xilinx Inc. This implementation achieves relatively higher data throughput at little cost of circuit resources, and forms a reusable IP core of AES Crypto Coprocessor.