基于FPGA技术的网络包头分类的研究

A research on packet classification based on FPGA

在基于FPGA技术的入侵检测系统的研究中,提出了一类结合三态内容可寻址内存(TCAM)和普通存储器(RAM)的网络包包头分类方案.将检测规则编号并位图化,使用RAM存储与包头结构相关的规则位图,通过TCAM上的数据匹配操作,快速关联待分析的网络数据包与入侵检测规则.在Quartus II 5.0上的仿真结果表明,时钟频率100 MHz下的片内分类速度达到1.8 Gbps.

In this paper, we develop a packet header classification method which combines TCAM and RAM. We compress and renumber the rules set and use the RAM to store the mapping of the compressed and the uncompressed rule set. Using TCAM operation and fast mapping operation, we can decide whether the packet match the rules. In our experiments, we show that throughput reach 1.8 Gbps under running at 100 MHz.