系统芯片IP核透明路径构建中的可测性分析

Testability Analysis for Transparency Paths Ready IP Cores in SoC

系统芯片的设计方法为测试技术带来新挑战。知识产权模块(IP核)测试访问机制成为测试复用的关键。构建IP核透明路径会对电路的故障覆盖率产生影响。基于门级透明路径的构建方法,通过分析插入电路的控制门和多路器的激活和传播条件,对路径构建对于IP核单固定型故障覆盖率的影响进行分析,给出可测性条件和故障覆盖率的计算公式,无需故障仿真即可估计构造透明路径后电路的故障覆盖率。通过故障仿真实验,证明该故障覆盖率的分析和计算方法是有效的。

The SoC design methodology introduces new testing challenges, and test access becomes a key demand for IP core test reuse. Transparency based test access mechanism may impact the test coverage of original circuits. This paper analyzes the fault stimulation and propagation conditions so as to conclude the testability impact of gate-level transparency paths construction, to the stuck-at fault coverage. Fault coverage can be calculated through the introduced testability analysis without extra fault simulation. The experimental results show the effectiveness and accuracy of the fault testability analysis and fault coverage evaluation.