期刊文献+

基于EPIC的同时多线程处理器取指策略

Instruction Fetch Policies for SMT Processors Based on EPIC
下载PDF
导出
摘要 EPIC硬件简单,同时多线程易于开发线程级并行,在EPIC上实现同时多线程可以结合二者的优点。取指策略对同时多线程处理器的性能有重要影响。该文介绍了几种有代表性的超标量同时多线程处理器取指策略,分析了这些策略在EPIC同时多线程处理器上的适用性,提出了一种新的适用于EPIC的取指策略SICOUNT。分析表明SICOUNT策略可以充分利用EPIC软硬件协同的优势,在选择取指线程时使用编译器所提供的停顿信息,能更精确地估计各个线程的流动速度,使取出指令的质量更高。 Explicitly parallel instruction computing (EPIC) can decrease the complexity of hardware, and simultaneous maltithread(SMT) has the unique ability to exploit TLP(Thread Level Parallelism), so great benefit can be obtained by combining these two techniques. Fetch policies are of great importance to the overall performance of SMT processors. This paper describes several prevailing fetch policies used in superscalar SMT processors, analyses their applicability for EPIC SMT processors, and proposes a novel fetch policy called SICOUNT (Stop ICOUNT) suitable for EPIC SMT. Detailed analysis indicates that SICOUNT strategy can take full advantage of the HW/SW Co-design characteristic of EPIC. It achieves this by taking into account the stop hints generated by EPIC compiler. This makes it easier for SICOUNT to evaluate the flowing speed of each thread more precisely, and to fetch instructions with better quality.
出处 《计算机工程》 CAS CSCD 北大核心 2007年第4期256-258,262,共4页 Computer Engineering
基金 国家"863"计划基金资助重大项目(2002AA110020) 国家自然科学基金资助项目(60273069)
关键词 显式并行指令计算 同时多线程 取指策略 ITANIUM SICOUNT Explicitly parallel instruction computing (EPIC) Simultaneous multithread(SMT) Fetch policy Itanium SICOUNT
  • 相关文献

参考文献5

  • 1Tullsen D,Eggers S,Levy H.Simultaneous Multithreading:Maximizing On-chip Parallelism[C]//Proceedings of the 22^nd Annual International Symposium on Computer Architecture.Santa Marg-heritaLigure,Italy.1995-06:392-403.
  • 2Tullsen D,Eggers S,Emer J,et al.Exploiting Choice:Instruction Fetch and Issue on An Implementable Simultaneous Multithreading Processor[C]//Proceedings of the 23^rd Annual International Symposium on Computer Architecture,PA,USA.1996-05:191-202.
  • 3Tullsen D,Brown J.Handling Long-latency Loads in a Simultaneous Multithreaded Processor[C]//Proceedings of the 34^th Annual ACM/IEEE International Symposium on Microarchitecture.,Texas,USA.2001-12:318-327.
  • 4Schlansker M S,Rau B R.EPIC:Explicitly Parallel Instruction Computing[J].IEEE Computer,2000,33(2):37-45.
  • 5Itanium Processor Microarchitecture Reference:for Software Optimization[Z].2000.http://www.developer.intel.com/design/ia64/itanium.htm.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部