摘要
In traditional universal asynchronous receiver transmitter （UART） controller, the data transmission is inefficient and the data bus utilization ratio is low. A novel design is provided to solve these problems. The architecture of the system is introduced, the flow charts of data processing as well as the implementation state machine are also presented in detail. This paper is concluded by comparing the performance of this design, which is realized on field programmable gate army （FPGA） using Verilog hardware description language （HDL）, with other traditional UART controllers.
In traditional universal asynchronous receiver transmitter （UART） controller, the data transmission is inefficient and the data bus utilization ratio is low. A novel design is provided to solve these problems. The architecture of the system is introduced, the flow charts of data processing as well as the implementation state machine are also presented in detail. This paper is concluded by comparing the performance of this design, which is realized on field programmable gate army （FPGA） using Verilog hardware description language （HDL）, with other traditional UART controllers.
基金
National Natural Science Foundation of China (60532030)
