针对任意位的CRC并行化方法及编解码器的实现

Implementation of parallel CRC approach of arbitrary bit length and encoder and decoder

介绍了一种基于查表法的针对任意位数据的任意位CRC并行计算的原理及算法,克服了现有的两类CRC并行算法延时大、毛刺多或仅适于2n位数据的2n位CRC校验的缺点。该方法使并行CRC校验的传输数据位数与CRC码位数之间的选择更灵活,并且在加速比、功耗和面积等方面具有优势。

This paper introduces the principles of a parallel CRC approach that fits arbitrary length of CRC for data with arbitrary width. This arithmetic is meaningful for UART or high speed serial communication like USB, which mostly transfer non -2^n - bit data with non - 2^n - bit CRC. The test result proves that this method takes advantages in the power consumption, speed- up rate and area.