AVS游程解码、反扫描、反量化和反变换优化设计

Hardware architecture optimizing for run lenth decoding, inverse scan,inverse quantization and inverse transform in AVS

提出了一种适用于AVS的游程解码、反扫描、反量化和反变换硬件结构优化设计方案。根据AVS整数变换和量化的特性,设计了可工作在不同模式的存储器阵列,既可用来进行反变换器所需的转置操作,又可用来存储中间结果,将游程解码、反扫描和反量化合并为一个流水线单元并行处理。该设计省去了存储中间结果所需的大量存储器,加快了处理速度,满足高清视频的处理要求。该设计通过了FPGA验证,综合结果表明,其逻辑门数仅为9076,最高工作频率大于200MHz。

An optimized hardware architecture of run lentil decoding, inverse scan, inverse quantization and inverse transform in AVS video decoder is presented. According to the specific integer transform and quantiza- tion algorithm used in AVS, a parallel memory array is designed to perform the transpose operation while pro viding a platform for a combined block - level pipeline stage, which integrated run length decoding, inverse scan and inverse quantization module together. This architecture resulted in higher processing speed and less intermediate memories and fulfilled the requirement of high definition video processing. The whole design has been verified by FPGA. The synthesis result shows that the gate count is only 9076 while the frequency is more than 200MHz.