基于对可编程逻辑块建模的FPGA通用装箱算法

Universal Packing Algorithm for FPGA Based on Logic Block Modeling

装箱是FPGA工艺映射中的最后一步流程。该文提出了一种全新的对FPGA可编程逻辑块进行功能级建模的方法,并给出了基于此建模的通用性装箱算法FDUPack。实验中应用该建模方法对几种不同类型的FPGA的逻辑块进行建模,并使用装箱算法将大量的测试电路装箱到这些不同的逻辑块中,经过与已有的针对某一特定结构的装箱算法比较,该算法体现了很好的通用性。

Logic block packing is the last procedure of FPGA technology mapping. A novel function level modeling method for programmable logic block is proposed. Based on this modeling, a universal logic block packing algorithm FDUPack is presented. In the experiment some logic blocks of different types of FPGAs are modeled, and by using the packing algorithm a lot of benchmarks are packed to these different types of logic blocks. Compared with the existent logic block specific packing algorithms, FDUPack is structure-independent and universal.