基于FPGA技术的新型膜片钳数字接口逻辑设计

The Logic Design in Digital Interface Based on FPGA for a Novel Patch-Clamp

为了满足膜片钳实验的需求,本课题设计了一种多通道的数据采集系统。它利用FPGA控制技术实现同步工作模式,即要求输入输出数据点与点在时间上对准;采样率在1kHz到350kHz范围内可调;8路ADC和4路DAC通道之间相互独立,并可以同时工作;本文将着重介绍FPGA控制逻辑部分的设计。

A multi - channel data acquisition and signal output system is designed to fulfill the requirement of the patch clamp system. The synchronization of data acquisition and signal output is accomplished by using the FPGA. The system comprises 8 analog input channels and 4 analog output channels, which can run simultaneously and independently and the sampling frequency is changeable in the range of 1 kHz to 350 kHz. Here the design of the system is presented, with the focus on the design consideration of the FPGA control unit.