摘要
对FPGA在图像处理器中的应用优势进行分析,提出异步FIFO的具体实现方案。在异步FIFO的具体实现中,读/写地址采用格雷码编码以解决空/满标志易出错问题;设计输入部分则采用了原理图和VHDL语言描述相结合的方式来提高电路工作频率。
The paper analyzes the advantage of FPGA's application in image processor, and the asynchronous FIFO's solution is brought forward. In the implementation of asynchronous FIFO, the read/write address chooses gray code to resolve the problem of empty/full flag; and in the design entry, the graphic editing combined with VHDL editing is chosen to improve circuit working frequency.
出处
《泰州职业技术学院学报》
2007年第3期9-11,共3页
Journal of Taizhou Polytechnic College