摘要
基于H.264/AVC的分像素点滤波算法提出了一种新的分像素插值结构,避免了大量中间数据的存储,并且具有数据流规整、控制简单、垂直方向连续插值、可重用等优点。在0.18μm工艺下,最大频率125MHz时,综合逻辑门数为18k门,能够满足SDTV(1280×720,30f/s)视频图像实时处理的需要。
This paper proposed a new interpolation architecture for sub-pixels based on H.264/AVC sub-pixel filtering arithmetic. This architecture greatly saved the storage need of the big amount of intermediate data; in addition, the control is simplified and is easy for hardware implementation. The synthesized logic gate count is only 18k under 0.18μm technology when the maximum frequency is 125MHz. This architecture can satisfy SDTV (1280×780,30f/s) video coding requirements.
出处
《微电子学与计算机》
CSCD
北大核心
2007年第7期187-189,193,共4页
Microelectronics & Computer
基金
湖北省自然科学基金项目(2006ABA087)