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H.264分像素插值滤波方法及其VLSI实现 被引量:4

Sub-Pixel Motion Estimation Interpolation Method and its High-efficient VLSI Implementation for H.264
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摘要 基于H.264/AVC的分像素点滤波算法提出了一种新的分像素插值结构,避免了大量中间数据的存储,并且具有数据流规整、控制简单、垂直方向连续插值、可重用等优点。在0.18μm工艺下,最大频率125MHz时,综合逻辑门数为18k门,能够满足SDTV(1280×720,30f/s)视频图像实时处理的需要。 This paper proposed a new interpolation architecture for sub-pixels based on H.264/AVC sub-pixel filtering arithmetic. This architecture greatly saved the storage need of the big amount of intermediate data; in addition, the control is simplified and is easy for hardware implementation. The synthesized logic gate count is only 18k under 0.18μm technology when the maximum frequency is 125MHz. This architecture can satisfy SDTV (1280×780,30f/s) video coding requirements.
出处 《微电子学与计算机》 CSCD 北大核心 2007年第7期187-189,193,共4页 Microelectronics & Computer
基金 湖北省自然科学基金项目(2006ABA087)
关键词 H.264/AVC 视频编码 分数运动估计 插值滤波器 VLSI H.264/AVC video encoding sub-pixel motion estimation interpolation filter VLSI
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参考文献4

  • 1Joint Video Team.Draft ITU-T recommendation and final draft international standard of joint video specification[M],ITU-T Rec.H.264 and ISO/IEC 14496-10 AVC,May 2003.
  • 2Deng Lei,Gao Wen,Hu Ming-Zeng,et al.An efficient VLSI architecture for MC interpolation in AVC video coding[C].Proceedings of the International Conference on Embedded Systems and Applications ESA'04-Proceedings of the INternational Conference on VLSI,VLSI'04,2004:564-568.
  • 3Chen Tung-Chien,Huang Yu-Wen,Chen Liang-Gee.Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC[J].Acoustics,Speech,and Signal Processing,2004.Proceedings.(ICASSP'04).IEEE International Conference,2004,5:9-12.
  • 4Yao Dong,Yu Lu.Sub-pixel interpolation of MPEG-4 motion compensation and its hardware implementation[J].Journal of Zhejiang University (Engineering Science),2005,11.

同被引文献32

  • 1卢佩,张正炳,刘效勇.运动估计中对不规则块匹配算法的理论研究[J].现代电子技术,2004,27(21):1-3. 被引量:4
  • 2钟麟.视频图像压缩质量检测方法[J].计算机与网络,2006,32(8):46-47. 被引量:2
  • 3HUANG Y W,CHIEN S Y,HSIEH B Y,et al.Global elimination algorithm and architecture design for fast block matching motion estimation[J].IEEE Trans Circ and Syst Video Technol,2004,14(6):898-907.6.
  • 4SHANBHAG N R.Reliable and energy-efficient digital signal processing[C] // DAC 2002.New Orleans,LA,USA.2002:830-835.
  • 5VARATKAR G V,SHANBHAG N R.Error-resilient motion estimation architecture[J].IEEE Trans VLSI Syst,2008,16 (10):1399-1412.
  • 6HUANG Y-W,CHEN C-Y,TSAI C-H,et al.Survey on block matching motion estimation algorithms and architectures with new results[J].J VLSI Sign Process Syst for Sign,Imag,Vid Technol,2006,42(3):297-320.
  • 7Shanbhag N R. Reliable and Energy - efficient Digital Signal Proeessing[A]. DAC 2002[C]. New Orleans, 2002 : 830 - 835.
  • 8Varatkar G V, Shanbhag N R. Error- Resilient Motion Esti- mation Architecture[J]. IEEE Trans. on VLSI Systems, 2008,16(10):1 399- 1 412.
  • 9Huang Y W,Chien S Y, Hsieh B Y,et al. Global Elimination Algorithm and Architecture Design for Fast Block Matching Motion Estimation[J]. IEEE Trans. on Circuits and Syst. Video Technol. , 2004,14(6) : 898 - 907.
  • 10Huang Y W,Chen C Y,Tsai C H,et al. Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results [J]. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 2006,42 (3) :297 - 320.

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