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一种用于音频DAC的可重构Σ-Δ调制器的设计 被引量：2

Design of Re-configurable Σ-Δ Modulator for Audio D/A converter
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摘要 设计了一种适于嵌入式FPGA应用的可重构Σ-Δ调制器,并采用高效的流水线结构实现,它能够被设置为3阶或5阶,可支持不同字长(16-/18-/20-/24-位)PCM数据的满幅输入。通过Matlab仿真,针对16位、44.1 kHz、过采样率为128的输入信号,工作在三阶情况下的调制器可以获得超过100 dB的信噪比(SNR);而在输入为24位1、92 kHz、过采样率为32时,工作在5阶情况下的调制器的信噪比(SNR)超过了150 dB,很好地抑制了通带内的噪声。 A re-configurable E-A modulator suitable for embedded FPGA application is designed, which can be configured as 3rd- or 5th-order SDM and accept 16-/18-/20-/24-bit PCM data input in full scale. Simulation using Matlab show that, for 44. 1 kHz, 16-bit input signal with 128 oversampling ratio, the modulator configured as 3rd- order can achieve a signal-to-noise ratio over 100 dB, and for 192 kHz, 24-bit input signals with 32 oversampling ratio, the modulator configured as 5th-order can achieve a signal-to-noise ratio over 150 dB.
作者 沈佳铭 洪亮 石春琦 赖宗声
机构地区 华东师范大学微电子电路与系统研究所
出处 《微电子学》 CAS CSCD 北大核心 2007年第3期432-435,439,共5页 Microelectronics
基金 上海-应用材料发展研究基金资助项目(AM-0513AM-0508)
关键词 Σ-Δ调制器 D/A转换器 过采样 可重构 ∑-△ modulator D/A converter Oversampling Re-configurable
分类号 TN792 [电子电信—电路与系统]
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参考文献6

  • 1Norsworthy S R,Schreier R,Temes G C.Delta-sigma data converters:theory,design and simulation[M].Piscataway,NJ:IEEE Press,1997.5-13.
  • 2Markus J,Silva J,Temes G C.Theory and applications of incremental ∑-△ converters[J].IEEE Trans Circ and Syst,2004,51(4):678-690.
  • 3Schreier R.An empirical study of high-order single-bit delta-sigma modulators[J].IEEE Trans Circ and Syst,1993,40(4):461-466.
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同被引文献13

  • 1闫华,杨军.一种用于数字音频的插值滤波器设计[J].现代电子技术,2007,30(6):1-3. 被引量：4
  • 2SCHREIER R, TEMES G. Understanding deltasigma data converters [M]. Piscataway :WileyIEEE Press, 2005: 443-446.
  • 3AMEUR N B, SOYAH M, MASMOUDI N, et al. FPGA implementation of polyphase decomposed FIR filters for interpolation used in ΔΣ audio DAC [C]∥ 2009 3rd International Conference on Signals, Circuits and Systems (SCS).Medenine:[s.n.],2009:1-13.
  • 4RAZAVI B. Design of analog CMOS integrated circuits [M]. New York: McGrawHill Inc, 2000.
  • 5EICHENBERGER C, GUGGENBUHL W. Dummy transistor compensation of analog MOS switches [J]. IEEE Journal of SolidState Circuits, 1989,24(4): 1143-1146.
  • 6BAIRD R T, FIEZ T S. Improved DeltaSigma DAC linearity using data weighted averaging [C]∥IEEE International Symposium on Circuits and Systems. Seattle,WA:IEEE,1995:13-16.
  • 7ANNOVAZZI M, COLONNA V, GANDOLFI G, et al. A lowpower 98dB multibit audio DAC in a standard 33V 035μm CMOS technology [J]. IEEE Journal of SolidState Circuits, 2002,37(7): 825-834.
  • 8程媛媛,杨文荣.音频数模转换器芯片内部低功耗的设计[J].计算机测量与控制,2007,15(11):1584-1586. 被引量：4
  • 9MARKUS J, SILVA J, TEMES G C. Theory and applications of incremental E-A converters [J]. IEEE Transactions on Cir- cuits and Systems, 2004, 51(4): 678-690.
  • 10COLODRO F, TORRALBA A, MORA J L. Digital noise- shaping of residues in dual-qnantization sigma-delta modulators [J]. IEEE Transactions on Circuits and Systems I: Regular Pa- pers, 2004, 51(2): 225-232.

引证文献2

微电子学
2007年 第3期

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