CESoP芯片实现方案及其专用集成电路设计

Design and implementation of application specific integrated circuit for CESoP

基于分组网络的电路仿真服务在分组网络上提供了一种传输传统电路交换业务的方法，对于现代网络融合具有重要意义。为了实现分组网络中的E1信号传送，提出一种分组电路仿真处理芯片的实现方案，并完成了芯片设计及应用试验。芯片实施协议符合IETF（internet engineering task force）PWE3（pseudo wire emulation edge—to—edge）工作组的相关建议草案，芯片内部集成全数字自适应时钟提取算法和服务恢复策略。目前基于该芯片方案的验证系统已经通过了10～100Mb以太网和802．11a无线网络的环境测试。结果表明：该实现方案能够有效抑制分组网络传输抖动和传输误码导致的服务失效，可以应用于多种网络环境。

Circuit emulation service over packet switched networks （CESoP） provides a seamless migration approach to packet switched network backbones without interruption of legacy services. This paper describes a new design scheme for a CESoP processing integrated circuit based on IETF （internet engineering task force） PWE3 （pseudo wire emulation edge-to-edge） standards to support E1 traffic transporting over packet switched networks. The circuit uses an all digital adaptive clock recovery algorithm and a service restoration scheme is included. Equipment based on this scheme was tested in a 10 ～ 100 Mb Ethernet and 802.11a wireless LAN application environment with the results showing that the scheme effectively reduces the transport jitter derived from the packet switched network and avoids service loss due to transmission errors. It can be used in multiple network environments.