摘要
介绍了基于可编程逻辑器件(CPLD)和直接数字合成技术(DDS)的虚拟信号发生器的整体设计方案.解决了通常任意波形发生器产生信号频率受CPU工作频率限制的问题,提高了信号频率,降低了成本.
The design of virtual signal generator based on CPLD and DDS technology is described. The signal frequency is not restricted in this virtual signal generator by CPU. This increases the frequency of the signal, and reduces the cost.
出处
《哈尔滨理工大学学报》
CAS
2007年第3期12-15,共4页
Journal of Harbin University of Science and Technology
