1GSPS高速数据采集时钟系统的设计

Design of Clock System in High Speed Data Acquisition

利用FPGA内部的锁相环进行1GSPS数据采集时钟系统的设计,提出了一种分相多路时钟的设计方法,并对设计方案进行仿真分析.设计方案合理利用可编程逻辑器件的内部资源,在不增加系统硬件成本的前提下,可以将设计方案灵活组态为双通道500MHz、4通道250MHz或8通道125MHz采样率的数据采集时钟系统.该时钟系统实现了外部时钟的片内管理,简化外部时钟电路和PCB电路板的设计.该项技术已成功应用到1GSPS数据采集系统中.

The plan of using the intemal phase lock loop of FPGA to generate the clock in 1 GSPS data acquisition is put forward, demux technology is introduced in this paper, and the simulation analysis is also done. Making use of the internal resource in FPGA reasonably, configurations of the clock system is flexible, and can be applied into the data acquisition system of two - channel 500MHz sample rate, four - channel 250MHz sample rate or eight - channel 125MHz sample rate, without increasing any hardware cost. In this way, in chip management of external clock can be implemented, clock circuit and the PCB design become simple. This technology is successfully put in-to the actual project of 1GSPS data acquisition system.