基于Verilog HDL设计线性分组编译码器

Verilog HDL Application for Complicated Circuit Design

针对传统电路图法设计复杂数字系统的周期长,需要专门的设计工具,需手工布线的缺陷,阐述了用Verilog HDL输入法在设计复杂电路方面的优势.并以线性分组码编译码器的具体设计实现说明了Verilog HDL设计的程序结构清晰,无需考虑具体电路的实现,大大减少了设计人员的工作量,提高了设计的准确性和效率.

To introduce Vefilog HDL which is used in digital system design the design procedure is illustrated. Moreover it shows the advantages of Verilog HDL at complicated circuit design by designing coder ＆ decoder of linear array code.