60Gbit/s宽带电路交换ASIC芯片设计

Design of ASIC chips for 60 Gbit/s broadband circuit switching

文章提出了一种60 Gbit/s宽带电路交换专用集成电路(ASIC)芯片的设计实现方案。针对设计芯片速度快、规模大和功耗大等特点,给出了采用流水线设计思想和优化结构处理技术的电路设计解决方案。同时还给出了采用现场可编程门阵列(FPGA)芯片对设计电路进行功能验证的结果和ASIC流片的基本数据。

This article presents a design scheme for ASIC chips used for 60 Gbit/s broadband circuit switching. A pipeline design concept and optimum structuring technology are put forward for fast-speed, large-size and high-power-consumption chips. The circuit functions are verified with altera FPGA chips and the results of the verification and its ASIC synthesis with Synopsys DC are given.