用正交多项式带限插值设计时变分数延迟线

Design of Variance-time Fractional Delay Line Based on Bandlimited Interpolation of Orthogonal Polynomial

提出了一种用于采样速率转换的时变分数延迟线算法,该算法是基于时域插值能量最小化,用构造的离散正交多项式进行带限插值。并讨论了利用延迟线实现实时采样率转换的方法。所提出的延迟线算法在Matlab下进行了仿真实验,说明了该算法是可行的。

This paper propose an efficient algorithm of variance-time fractional delay line for sampling rate conversion （SRC）, which implements bandlimited interpolation employed orthogonal polynomial based on minimum the energy of approximation in time domain. And realtime SRC method is discussed. A simulation in matlab validate the algorithm.