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0.65V 3mW CMOS低噪声放大器设计 被引量：1

Design of 0.65 V 3 mW CMOS LNA
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摘要 给出了工作电压为0.65 V,功耗仅为3 mW的低噪声放大器设计。设计采用TSMC 0.18μm RF CMOS工艺完成。最终的电路仿真结果显示,在0.65 V的电源电压下,S21达到17 dB,S11小于-11 dB,噪声系数小于2.2 dB,线性度指标IIP3为-11.6 dBm。 A LNA work with low voltage of 0. 65 V and consume only 3 mW Power is introduced in this paper. It is completed in TSMC 0.18 μm RF COMS process. And the simulation results show that the S21 is 17 dB,S11 is under -11 dB,NF is smaller than 2.2 dB, IIP3 is -11.6 dB.
作者 殷蔚
机构地区 岳阳职业技术学院
出处 《现代电子技术》 2007年第15期104-106,共3页 Modern Electronics Technique
关键词 低电压 低功耗 低噪声放大器 CMOS low voltage low power LNA CMOS
分类号 TN72 [电子电信—电路与系统]
  • 相关文献

参考文献12

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二级参考文献7

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共引文献22

同被引文献13

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现代电子技术
2007年 第15期

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