摘要
In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.
In this letter, a scheduling scheme based on Dynamic Frequency Clocking （DFC） and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.
基金
the Natural Science Foundation of Hei- longjiang Province, China (F2004-17).
关键词
调度安排
动态频率时钟
电压
资源约束
Scheduling scheme
Dynamic Frequency Clocking （DFC）
Multiple voltages
High level synthesis
