采用限制电流和固定分时控制的DC/DC转换器设计

Design of DC/DC Converter Controlled by Limited Current and Constant Off-Time

为了使设计的DC/DC转换器在宽负载范围内能保持高效率和高性能的输出电压,基于典型脉冲频率调制转换器拓扑结构,提出一种在不同升压阶段,由可调整的限制电流和固定分时控制的DC/DC转换器芯片的设计.本设计基于标准的0.6μm BiCMOS混合信号工艺,采用Cadence/Spectre仿真,最终实现转换器效率高于80%,最高为20 V的可调节输出电压,并且其相对纹波系数小于1%.

Keeping high efficiency and perfect output voltage （Votrr） in wide range of loads, a DC/DC Converter which controlled by different limited current and constant off-time during different Votrr rising step, is designed on the basis of typical pulse frequency modulation （PFM） DC/DC converter topology. The design is implemented in a standard 0. 6/,m BiCMOS mixed-signal process and simulated with Cadence/Spectre. At last, we design the converter successfully, and its efficiency η〉80%, VOUT（max） =20 V, and ripple=ΔVOUT/VOUT〈1%.