一种基于流水线的MQ编码器FPGA设计

FPGA Design of Pipeline-Based MQ Coder

提出了一种应用于JPEG2000标准的4级流水线MQ编码器设计方案.采用状态超前更新,前导0位超前检测和字节输出缓冲策略,解决了在上下文(CX)状态表更新、归一化及字节输出过程中的反馈和循环等问题,提高了编码效率.同时,对关键路径处算法进行优化,提高了系统工作的时钟频率.该设计使用VHDL语言在RTL级描述,并在FPGA上对其进行了仿真验证.实验表明,在Altera的StratixII EP2S601020C4上,编码器的工作效率可以达到1CxD/cycle,最高工作时钟频率可达99.66 MHz.

A four-stage pipelined architecture MQ coder for JPEG2000 standard is presented. To solve the problem of feedback in the conventional MQ coder in JPEG2000, we used a new method of updating CX table. Through the technology of leading zero forwarding detection and byte out buffer we improved the efficiency of encoding. In addition, we optimized the arithmetic of critical path and then increased the clock rate of the system. We have implemented the design in VHDL RTL on the FPGA. Experimental result shows that the new MQ coder can process one symbol per clock cycle and can work up to 99.66 MHz on Altera＇ StratixII EP2S601020C4.