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基于MASH 2-1结构的小数分频锁相环的设计与实现

Design and Implementation of Fractional-N PLL Based on MASH 2-1 Architecture
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摘要 设计并实现了一种3阶多级累加器级联架构MASH 2-1的数字Δ∑调制器.Matlab仿真结果显示该结构具有良好的噪声整型特性.提出了一种基于MASH 2-1Δ∑调制器的II型4阶锁相环,并给出了相应的Matlab仿真及频谱仪测试结果.结果表明锁相环的稳定输出频率符合设计要求. A digital Δ∑ modulator with a three-order MASH (Multi-Stage noise SHaping) 2-1 architecture is designed and implemented, whose advantages in noise shaping is then verified by the results of Maflab simulation. Then, a type-Ⅱ four-order phase-locked loop (PLL) employing the Δ∑ modulator based on MASH 2-1 is presented. According to the results of the corresponding Matlab simulation and the frequency spectrum measurement, it is found that the stable output frequency of PLL meets the design requirement.
出处 《华南理工大学学报(自然科学版)》 EI CAS CSCD 北大核心 2007年第6期50-53,75,共5页 Journal of South China University of Technology(Natural Science Edition)
关键词 MASH Δ∑调制器 小数分频 锁相环 Multi-Stage noise SHaping Δ∑ modulator fractional-N phase-locked loop
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参考文献10

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