摘要
以500 V VDMOS为例,首先分析了高压VDMOS导通电阻与电压的关系,重点讨论穿通型VDMOS的外延厚度与器件的耐压和导通电阻的关系。给出对高压VDMOS外延层厚度的优化方案,并基于理论分析在器件仿真设计软件平台上成功完成了耐压500 V、导通电阻0.85Ω的功率VDMOS器件的设计和仿真。
Taking an example for 500 V VDMOS, we analyze the relationship between on - resistance and voltage of VDMOS,and study the relationship between the depth of epitaxial layer of punch -through VDMOS and breakdown voltage,onresistance in detail. Bring forward a scheme to optimize the depth of epitaxial layer of high voltage VDMOS,and simulate the VDMOS of 500V breakdown voltage and 0.85 Ω on - resistance.
出处
《现代电子技术》
2007年第16期174-176,共3页
Modern Electronics Technique
