一种自偏置低压共源共栅带隙基准电路设计

Design for a Self-bias Cascode Bandgap Reference

随着CMOS工艺的发展,器件尺寸逐渐缩小,短沟道效应的影响日益突出。共源共栅电流源可以很好地抑制小尺寸效应,但其消耗的电压余度较大,偏置电路设计繁琐。因此介绍了一种采用自偏置低压共源共栅电流源的带隙基准电路结构,用两个电阻代替了偏置电路。仿真结果显示,该带隙基准电路的最低电源电压约为2.98V,相对于普通的共源共栅结构,降低了2个MOSFET阈值电压;工作在最低电源电压下,功耗约为270μW,相对于带偏置电路的结构,降低约75μW。仿真结果证明,该电路能够简化共源共栅电路的设计和调试,并减少低压共源共栅电路的功耗。

As the development of CMOS technology, the size of elements was shorten more and more, and Short-Channel Effects was more notable than before. Cascode structure could restrain these effects, but there was a big dissipation on voltage margin, and fussy design. This paper introduces a low supply voltage band-gap reference circuit which used a self-bias cascode current mirror. This structure used tow resistors to replace bias circuit. Relative to normal cascode current mirror, this structure have lower voltage by one MOSFET threshold voltage, come up to 2.98V; the power dissipation is 270μW, which is lower than the structure with bias circuit by 75μW. The simulation results listed above prove that, this structure could simplify the design and adjustment of bias circuit greatly, and lower the power dissipation of low-voltage cascode structure.