低管脚数接口在USB2.0主机控制器中的应用

Low Pin Count Interface for USB2.0 Host Controller in SOC System

在复杂SOC设计中,通常外围众多的输入输出单元会造成芯片总面积较大、后续封装和布局的成本提高。针对该问题分析了一种通用的低管脚数优化设计模型,将其应用于USB2.0主机控制器的链路层和物理层接口,用Verilog硬件描述语言实现了RTL级电路并做FPGA验证。通过数据分析表明,该设计有效地降低了芯片的总面积和制版复杂度,达到了设计目标。

In Complicated SOC design, usually excessive I/O PAD amount would greatly enlarge the total chip area and increase the cost of layout and packaging. In this paper, general LPC （Low Pin Count）model is analyzed and applied to the interface between Link and PHY of USB2.0 host controller. Verilog HDL in RTL level of the circuits are synthesized and then verified on FPGA board. The result shows that by adopting ULPI model, total area and back-end complexity are both expectedly decreased.