超低成本的AES算法VLSI实现

Very Low-cost VLSI Implementation of AES Algorithm

提出一种超低成本的先进密码算法(AES)的VLSI实现方案.为了尽量减小硬件开销,将每轮128位的加解密运算分成4次32位运算,以两级流水线结构实现,同时通过模块复用和优化运算次序,特别是提出了一种低成本的密钥扩展结构,以很小的硬件代价获得很高的性能.本设计采用HHNEC0.25um标准CMOS工艺,单元面积仅约12k等效门;在100MHz工作频率下,128位加密的数据吞吐率达到256Mbps.

This paper proposes a very low-cost VLSI implementation of AES algorithm. This design splits the 128bit computation in every round into four 32bit calculations and exploits 2 level pipelines to finish the process. Moreover, such improvements as module reuse and calculation order optimization, especially low-cost key expansion architecture, are used to achieve high performance with very low hardware cost. Using the HHNEC 0.25um CMOS process, the scale of the design is about 12K equivalent gates and its system frequency is up to 100MHz. The throughputs of the 128bit dada encryption and decryption are as high as 256Mbit/s.