32位高性能DMA控制器的VLSI实现

VLSI Design of 32-bit High Performance DMA Controller

高性能的DMA控制器是诸如高端微处理器和媒体处理器等SoC片上通信架构的重要组成部分。该文提出了面向AMBA总线的高性能32位DMA控制器的VLSI实现,引入了双时钟域、同步复位门控时钟和握手信号路由阵列的设计。在SMIC0.18μm的工艺下,可以达到180MHz的工作频率。应用于32位RISC处理器ALP3310中,与使用软件传输相比,AHB总线和APB总线的数据传输速度分别提高80.0%和26.7%。

A high performance DMA controller is an important component of the onchip communication architecture of SoCs such as advanced microprocessors and media processors. This paper presents a VLSI design of an AMBA-oriented 32-bit high performance DMA controller, involving dual clock domain, gated clock with synchronous reset and handshake signal routing array design. With 0.18μm library technology of SMIC, a working frequency of 180MHz is achieved. In RISC processor ALP3310, compared with transfer by software, DMA increases data transfer speed by 80.0% and 26.7% on AHB bus and APB bus respectively.