基于FPGA的RFID数字接收机的设计

Design of RFID Digital Receiver Based on FPGA

提出了一种全新的射频识别(RFID)数字接收机的实现方案。针对RFID系统实时性的要求,该设计采用简化的相关算法取代数字锁相环结构,快速准确地捕获频率范围在31.2kHz-780.8kHz内的突发信号,并实现接收数据解码。与采用过零检测方案的数字接收机相比,本设计具有更强的抗干扰能力。该数字接收机在Altera Stratix II EP2S60上验证通过,取得了良好的性能。

A novel design of RFID （radio frequency identification） digital receiver is presented. In order to meet the real time requirement for RFID system, this paper uses simplified correlation algorithm instead of the DPLL （digital phase lock loop） structure. The receiver can adaptively capture the burst mode input signal ranged from 31.2kHz to 780.8kHz and finish the decoding process. The design is more robust to noise interference compared with that using the zero crossing method. The digital receiver is implemented on Altera Stratix Ⅱ EP2S60 and has great performance.