摘要
介绍了数字电视广播中广泛采用的RS(204,188)译码器原理和FPGA实现方案,采用并行的三级流水线结构以提高速度,并根据Berlekamp-Massey(BM)算法对译码器进行了优化设计,减少了硬件消耗。译码器的最大时钟频率可以达到75MHz。译码器的性能仿真和FPGA实现验证了该方案的可行性。
A RS（204,188 ） decoder is implemented with FPGA at 75 MHz clock frequency, which is widely applied in digital video broadcasting （DVB） receivers. The 3 - stage pipeline architecture is adopted to increase speed. The decoder is optimized to reduce hardware consumption according to Berlekamp- Massey （BM） arithmetic.
出处
《电讯技术》
2007年第4期152-155,共4页
Telecommunication Engineering
