多电源系统的版图设计

The Layout Design of Muti-power Network

随着工艺尺寸的减小,电源电压也随之降低,芯片内部产生不同的电源级别。如何设计好这个复杂的电源网络,是目前设计者越来越关心的一个问题。文中从基于0.25μm CMOS工艺的SRAM出发,从整体布局及可靠性等多个方面阐述了多电源系统的版图设计,同时介绍了电源管理模块(VDC)设计上的一些结构和技巧。

With the scaling of technology, the power voltage also drops, it causes different voltage grade on chips. Now more and more designers pay attention to this problem that how to design such complex power network reasonable. This paper is based on 0.25 μ m CMOS technology SRAM, It describes the layout design about muti-power network from path approach and realiabity, and so on. It also present to us some advice and skill on VDC design.