FPGA的布线开关和互连线段的优化设计

The Optimized Design of Routing Switch and Wire Segment of FPGA

文章以TSMC'0.35μm,三层金属CMOS工艺为基础,对FPGA互连资源中布线开关和互连线段进行了具体分析。研究表明,布线开关中同时混合使用传输门和三态缓冲器以及采用不同逻辑长度的互连线段组合时将会产生较好的面积-延时值。

The routing switch and wire segment of interconnect resource FPGA have been analyzed concretely based on TSMC＇ 0.35 μ m, three-layer metal CMOS process in this paper. The results show that employ the different logic length wire segmentation distributions and the best mixes of pass transistors and tri-state buffer switches found in this paper bring more area-delay product.