摘要
研制了一种采用0.13μm混合信号CMOS工艺的高速USB2.0收发器.为适应工艺和系统指标的要求,改进了高速电流模式差分比较器,带跳变窗口使能逻辑鉴相器和模拟连续调整共模反馈电路等电路模块的设计.电路在SMIC流片后经测试,结果表明预期功能均得以实现,发送数据抖动(方均根)小于53ps,接收误码率小于10-12,电源电压为1.2V,功耗为42.5mW,芯片面积为900μm×700μm.
A USB 2.0 high speed transceiver was designed in 0.13μm mixed-signal CMOS technology. A high-speed currentmode differential comparator, a phase detector with window-enabling logic, and an analog continuously-adjusting CMFB were developed to meet the specifications and 0.13μm technology. The transceiver has been fabricated in SMIC. The transmitterjitter was 53ps,and the bit error rate of the receiver was less than 10^-12. The power consumption was 42.5mW at a power supply of 1.2V, and the chip area was 900μm× 700μm.
关键词
高速差分比较器
锁相环
环路滤波器
共模反馈
differential envelope detector
phase locked loop
loop filter
common mode feedback
