基于FPGA的分布式算法FIR滤波器设计

Design of digital FIR bandpass filter using distributed algorithm based on FPGA

FIR滤波器具有许多优点,是数字信号处理系统中基本的元件。本文比较了目前FIR滤波器硬件实现的几种方法,详细研究了基于FPGA、采用分布式算法实现FIR滤波器的原理和方法,设计了一个32阶线性相位FIR滤波器,并用VHDL语言对其进行了描述。此滤波器采用串行加法器将数据进行预相加,从而将滤波器的规模减半。其主要部分——乘累加单元,采用LUT查找表结构,将乘法运算转换为查表操作,提升处理速度。最后进行了硬件仿真,结果证明,这一方法是可行且高效的。

The FIR filter has a lot of merits, so it is the basal component of the DSP system. In this paper, after several methods to realize FIR Filter are compared, the theory and method to realize FIR Filter using Distributed Arithmetic based on FPGA is presenteck A 32-tap linear phase FIR Filter is designed, and described with VHDL. In which, the data is pre-added by the serial adder in advanced, thereby, the size of filter is halved. The chief part of FIR filter is multiplication-accumulation part, and it adopts LUT structure based on the Distributed Arithmetic principle, which conveys multiplication to checking table to improve the processing speed. Finally, the hardware simulation is made, the results prove that this method to be capable and high effective.