摘要
以DVB-H系统为例对载波同步算法提出了一种硬件实现架构。为易于硬件实现,对小数倍频偏估计采用了一种通过整数倍频偏估计修正与估计值自平均相结合的算法,同时在频偏估计中通过资源复用,大大节省了硬件资源,提高了硬件工作速度。
In this paper, a VLSI architecture for carrier synchronization is proposed using DVB-H as an example. For the easy implementation on FPGA, the fractional part of the carrier frequency offset is estimated by the integer part of the carrier frequency offset adjustment combining with average of itself. At the same time, in this hardware structure a lot of resources are used repetitively. Totally, a hardware structure design with few resources and high speed is realized.
出处
《电视技术》
北大核心
2007年第8期35-38,共4页
Video Engineering
