Turbo码快速交织算法的性能仿真及其FPGA实现

Simulation of Fast Interleave Algorithm for Turbo Codes and Implementation Based on FPGA

针对目前交织器存在的时延大的缺陷,设计了一种基于短时延伪随机序列的Turbo码快速交织算法,给出了基于FPGA的硬件实现方案,在时延和性能之间取得较好的折衷。仿真结果表明,该交织算法在不增加Turbo码编译码复杂度的情况下,一次迭代过程交织模块即能减少20%的时间延迟。

This paper proposes a fast interleaver algorithm based on the pseudo-random sequence with the shortest latency after analyzing the drawback of current interleavers and also presents the implementation based on FPGA. It achieves a tradeoff between the latency and the performance. The analyzing results show that this interleaver could reduce the latency up to 20% during one iterative process without adding complexity.