基于FPGA的DPLL设计与仿真实现

Design and analyze digital PLL on FPGA

本文分析了超前滞后型数字锁相环(LL-DPLL)的基本组成和工作原理,用VHDL语言对该系统进行了设计,给出了数字锁相环电路3个主要模块的设计方法及仿真结果,得到了该系统的顶层电路,最后根据整个系统的仿真结果分析了系统的稳态性能。整个系统的锁相环部分达到了锁定速度快、相位抖动小、锁定精度高的结果。

This paper gives a introduction to the composing and principle of lead-lag Digital Phase Locked Loop （LL-DPLL）, and discuss how to use VHDL language to design this system. It presents the design method and simulation result of 3 main modules, and then gets the top circuit. Finally it gives the analyse of the stability of this system based on the simulation result of it. Furthermore the quality of system appears quick launching , small errors and high precision.