高速CMOS可编程分频器的研究与设计

Design and Research of CMOS Programmable Divider

本文通过对CMOS可编程分频器原理的分析与研究,提出了一种新的可实现任意分频的可编程分频器结构,这种结构大大提高了可编程分频器的输入带宽,同时功耗不大,抗干扰能力强,可适用于锁相环、频率综合器的设计中。该设计在宏力CMOS0.18um工艺下通过仿真和验证,输入频率可以达到3.3GHz。

This paper studies the CMOS programmable divider and proposes an improved structure to get 2-32 random frequent division and increase the input frequent band width, input frequent gets to 3.3GHz in Grace CMOS 0.18um technology. At same time, it can reduce the power cost and the influence of noise.