数字锁相位同步提取的VHDL实现

Implementation of Digital phase-locked Bit Synchronous extract based on VHDL

本文设计了一种在数字通信系统中的数字锁相位同步提取方案,详细介绍了本设计的位同步提取原理及其各个组成功能模块的VHDL语言实现,并在QuartusII开发平台上仿真验证通过。本设计采用VHDL语言编程且在FPGA芯片上实现,具有可移植性好、体积小、低功耗、可靠性高、方便维护和升级等优点,增强了系统的可靠性和稳定性。经验证该位同步提取设计方案能够快速的提取位同步时钟,稳定性好。

This article has designed one kind of digital phase-locked bit synchronous extraction project in the digital communication system, introduced bit synchronous extraction principles and VHDL language realization of each composition function module in detail, and have passed the simulating in the development platform -Quartus Ⅱ. This design is achieved in a FPGA chip using VHDL language to program. It has the merits of good transplant,small size ,low-power consumption,high reliability,facilitate to maintain and upgrade, and so on ... enhanced the reliability and stability of digital communication system. This design can complete bit synchronous clock extraction rapidly and good stability after confirmation.