一种基于嵌入式ADC应用的运算放大器IP核

Design of Operational Amplifier IP Core for Embedded A/D Converters

介绍了一种适用于嵌入式模拟/数字转换器(ADC)应用的全差分低功耗性能可调运算放大器IP核。该运放芯核采用TSMC 0.25μm标准数字CMOS工艺设计。基于BSIM3V3 Spice模型,采用Hspice在2.5 V单电源电压下,分别对整个电路在几组不同的偏置条件下进行仿真,其中一组偏置在低频增益为74 dB,相位裕度为60°,单位增益带宽为107 MHz,摆率为210 V/μs时,整个电路的静态功耗仅为1.75 mW。

Based on embedded ADC application, a low power fully differential operational amplifier IP core with reeonfigurable performance is presented. The operational amplifier was realized in TSMC＇s 0. 25 μm 1P5M CMOS process. Based on BSIM3V3 Spice model, the whole circuit was simulated using Hspice with a single power supply of 2. 5 V under different bias conditions, it has been shown that, in one bias condition, the operational amplifier has an open loop gain of 74 dB, a phase margin of 60°, a slew rate of 210 V/μs and a unit gain bandwidth of 107 MHz, while dissipating only 1.75 mW of static power.