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基于0.18μm CMOS工艺的超高速比较器 被引量：5

0.18 μm CMOS Ultra High-Speed Comparator
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摘要 给出了基于TSMC 0．18μm CMOS工艺的1．8V超高速比较器的设计方案；对比较器速度和失调进行综合，设计了一个1GHz超高速低失调比较器；通过Monte Carlo仿真，验证该比较器的失调电压分布范围为-4．5～4．5mV，并进行了版图设计。该比较器应用于低电压A／D转换器设计中，可达到6位以上的精度。 Based on TSMC＇s 0. 18 μm CMOS process and 1.8 V power supply, an architecture of ultra highspeed comparator was proposed. With both speed and offset voltage taken into consideration, a 1 GHz high-speed low-offset comparator was designed. Monte Carlo simulation was performed to verify the offset voltage, which was from around -4. 5 mV to 4. 5 mV. The circuit could be used in high-speed low-voltage A/D converters to realize 6- bit resolution.
作者 高彬 孟桥 沈志远
机构地区 东南大学射频与光电集成电路研究所
出处 《微电子学》 CAS CSCD 北大核心 2007年第4期599-602,共4页 Microelectronics
基金 国家自然科学基金资助项目(60576028)
关键词 超高速比较器 A/D转换器 MONTE Carlo仿真 失调电压 Ultra high-speed comparator A/D converter Monte Carlo simulation Offset voltage
分类号 TN752 [电子电信—电路与系统] TN432 [电子电信—微电子学与固体电子学]
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参考文献8

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二级参考文献12

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共引文献6

同被引文献25

  • 1BOGATIN E.信号完整性分析[M].李玉山李丽平,译.北京:电子工业出版社.2009.
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  • 3Allen Philip E. CMOS Analog Circuit Design[M]. 2nd ed.北京:电子工业出版社,2003.
  • 4Mehdi Banihashemi, A High-speed high-resolution Comparator[C]// The 47th IEEE International Midwest Symposium on Circuits and Systems. Hiroshima: IEEE, 2004, :81-84.
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  • 7WUDY, ADC with technology 2011, 32 ZHOU L, GUO J N, et al. A 4 GS/s4 bit 3.8 GHz analog bandwidth in GaAs HBT [J]. Chinese Journal of Semiconductors, ( 6 ) : 065007-1 - 065007-7.
  • 8RAZZAGHI A. A single-channel 10 b l GS/s ADC with 2-Cycle Latency using pipelined cascaded folding architecture [ D]. USA : University of California, 2008 : 29 -35.
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  • 10KUO W M L, LI X T, KRITHIVASAN R. A 32 GS/s SiGe HBT comparator for ultra-high-speed analog-to- digital conversion [C] //// Proceedings of Microwave Conference. Su zhou, China, 2005, 5 (12) : 4 -7.

引证文献5

二级引证文献4

微电子学
2007年 第4期

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