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工艺参数变化下的基于统计时序分析的时钟偏差安排 被引量：1

Statistical Timing Analysis Based Clock Skew Scheduling in Presence of Process Variations
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摘要 针对工艺参数变化的情况,提出一种成品率驱动的时钟偏差安排算法.提出统计时序约束图的概念,利用统计时序分析的结果将时序电路转换为统计时序约束图;将寻找关键环问题转换为最小费用/时间比值环问题,并按比例分配关键环中的时钟偏差的安全余量.实验结果表明,该算法有助于提高集成电路的成品率. A yield driven clock skew scheduling algorithm is proposed in presence of process variations. Firstly,we present the concept of statistical timing constraint graph and transform a sequential circuit into a statistical timing constraint graph by using the result of statistical timing analysis. Then, the slacks are assigned proportionally in the critical cycles, which are detected iteratively using the algorithm for minimum cost-to-time ratio cycle problem. Experimental results show that the algorithm can help with is improving the yield of integrated circuits.
作者 方君 陆伟成 赵文庆
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2007年第9期1172-1177,共6页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金(90307017 60676018) 国家"九七三"重点基础研究发展规划项目(2005CB321701) 教育部跨世纪优秀人才培养计划基金 教育部博士点基金(20050246082) 上海市科委重点基础研究项目(04JC14015 05JC14007) 上海应用材料研究与发展基金(0418).
关键词 时钟偏差 统计时序分析 统计时序约束图 成品率 clock skew statistical timing analysis statistical timing constraint graph yield
分类号 TN47 [电子电信—微电子学与固体电子学]
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参考文献14

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共引文献10

同被引文献19

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引证文献1

计算机辅助设计与图形学学报
2007年 第9期

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