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一种2.5Gbit/s信号发生器的设计与实现

Design and realization of a 2.5Gbit/s signal generator
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摘要 设计并实现了一种2.5Gbit/s的信号发生器。利用锁相环技术将155.52MHz的信号倍频到2.5GHz,再把该信号作为时钟输入到伪随机序列发生模块中,得到了速率为2.5Gbit/s的伪随机序列输出。测试结果表明信号发生器的输出速率稳定在2.59Gbit/s,信噪比为21.34dB。而且该信号发生器具有价格低廉,结构紧密,使用方便的特点。 In the present paper, a 2. 5Gbit/s signal generator is designed and realized. Based on phase locked loop (PLL) technique, a 2. 5GHz clock signal is generated by multiplying a 155( 52 MHz source signal, and then inputted into -random bit sequence generation module to achieve the 2.5Gbit/s pseudo-random bit sequence signal. Testing results indicate that the output speed of the signal generator is stable at 2.59Gbit/s and the signal to noise ratio (SNR) is 21.34dB. In addition, this signal generator has the advantages of low cost, compactness, and convenience.
出处 《光学仪器》 2007年第4期57-61,共5页 Optical Instruments
关键词 信号发生器 高速时钟 锁相环(PLL) 伪随机二元序列 signal generator high-speed clock phase locked loop (PLL) pseudo-random bit sequence
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