利用FPGA设计与实现直接数字频率合成器

Design of DDFS based on FPGA and its implementation

现代直接数字频率合成技术在通信及信号处理中应用广泛。使用FPGA的设计方案较之专用芯片有着设计灵活、可定执行强的特点。介绍了在FPGA中实现DDFS的算法原理以及如何结合PLD设计的优化方法选取合适的设计参数,并最终通过VHDL语言和Quartus II软件在Altera公司的ACEX EP1K30器件上的设计实现过程。设计使用Quartus II软件完成时序仿真,并使用MATLAB编写了最终的模拟仿真程序。

Direct digital frequency synthesis is used widely in communication and signal processing. The design of DDFS with FPGAs is much flexible and programmable than special CMOS chip. This paper introduces the arithmetic principle of DDFS with FPGA and it also presents how to select the parameters which can improve system capability with PLD optimization method. This design implements the DDFS logic with VHDL and Ahera ACEX EP1K30 device and finishes the timing simulation in Quartus II software. Finally the simulation program is given by the Mathworks MATLAB language.