可编程逻辑器件逻辑功能的测试新方法

A New Designed Method For the Logical Function Test of PLD

以GAL16V8为例介绍了一种对可编程逻辑器件逻辑功能的测试方法,其中硬件接口电路采用了增强型并行口,使传统的并行口具有高速双向数据传输的能力。由于GAL16V8中设计了加密位,从而无法直接读取其内部控制字,软件中用“应用代替测量”,使其用应用的有效形式却兼有测量的效果。

This paper introduces the circuit designed for the logical function test of PLD （programmable logic device） based on the GAL16V8.By using EPP, the circuit gets the capability of bidirectional data transmission at high speed, comparing with the traditional parallel interface. Due to the existence of enerypt bit in the GAL16V8, we cannot directly read its inside control bits. So we verify the PLD＇s function test via its application in the circuit.