专用指令分组密码微处理器体系结构研究

Architecture of Block Ciphers Processor Based on Specific Instruction-Set Research

本文以分组密码算法为研究对象,结合微处理器体系结构的特点,研究能够高效灵活实现多种分组密码算法的处理器体系结构。论文通过分析现有分组密码算法结构特点,从实现方式的灵活性和高性能角度出发,提出了一种基于专用指令集的分组密码微处理器的设计思路,并给出了分组密码微处理器的运算单元设计方案及整体系统架构。

Based on existing block ciphers and combined with characteristic of processor architecture, this paper has a research on high performance processor architecture for block cipher algorithms. Through analyzing the flexibility and speed of existing implemen- tation methods, a block ciphers processor architecture is presented, and also an optimum method of the operation unit design is given.