SRAM型FPGA的抗SEU方法研究

Research on SEU Mitigation of FPGA Based-on SRAM

通过分析静态随机访问存储器(Static Random Access Memorg,SRAM)型现场可编程门阵列(Field Programable Gate Array,FPGA)遭受空间单粒子翻转(SEU)效应的影响,并比较几种常见的抗SEU技术:三模冗余(Triple Module Redwcdancy,TMR)、纠错码(Error Correction Code,ECC)和擦洗(Scrubbing),提出了一种硬件、时间冗余相结合的基于双模块冗余比较的抗SEU设计方法。在FPGA平台上对线性反馈移位寄存器(Linear Feedback Shift Register,LFSR)逻辑进行软件仿真的抗SEU验证实现,将各种容错设计方法实现后获得的实验数据进行分析比较。结果表明,64阶LFSR的抗SEU容错开销与基于硬件的TMR方法相比,可以节省92%的冗余逻辑资源;与基于时间的TMR相比,附加时间延迟缩短26%。

A new method to mitigate SEU on FPGA based-on SRAM, named DMRC, was proposed by analyzing the influences of SEU on FPGA based-on SRAM and comparing with several common mitigation techniques： Scrubbing, ECC and TMR. By validation baced-on simulation software of On-Borad FPGA, it was proved that the new method mitigating SEU on the 64-taps LFSR saved 92% redundant logic elements and shortened 26% additional delay comparing with hardware-based TMR. Thus, the method reduced greatly the cost of fault-toletant design.