一种嵌入式微处理器cache存储体系结构设计

An on-chip cache design of an embedded microprocessor

本文介绍了一种基于32位整数单元的片上cache存储体系结构设计的方案。作为SOC平台的核心部件,本设计中所有模块均自行设计,采用自顶向下的设计方法,应用Verilog HDL硬件描述语言进行设计,总线接口符合AMBATM总线规范(Rev 2.0)。为了对设计功能的有效性进行验证,还设计了一个基于AMBATM总线协议的通用SOC的系统虚拟验证平台,利用该平台对相关模型进行了调试和仿真。仿真结果表明,设计达到预期的功能要求。

This paper introduced a scheme of on-chip cache structure design based on a 32- bit Integer Unit. As the core unit of SOC platform, all modules were designed by utilizing the top-down method with Verilog HDL. All the interfaces were accorded with AMBA Specification （Rev 2.0）. For the validation verification of the functionality of the design, a virtual verification platform of a common SOC platform based on AMBA protocol was also designed, on which the corresponding models were debugged and simulated. Simulation results showed that the design matched the expected functional desires.