一种基于混合频率的微处理器设计方法

A Multi-Frequency Based Methodology for Microprocessor Design

为了在微处理器结构优化的同时保持合理的硬件开销,提出了一种混合频率策略.它允许流水线模块根据各自逻辑复杂度选择不同的工作频率;通过提高简单模块的工作频率,并增加复杂模块的并行度,以实现流水线的指令吞吐率的优化.实验表明,相比商业化的处理器,该策略下的超标量结构在保持电路和功耗开销的同时,指令吞吐率平均有23%的提高.

In order to achieve architectural optimization with acceptable hardware overhead for embedded microprocessor, a novel multi-frequency clock scheme was proposed. It applies multiple clocks on different pipeline parts basing on their logic complexity, and provides a parallelism on the slow part for throughput compensation. Compared to its commercial counterparts, the proposed scheme can improve the instruction throughput by 23%, while maintaining the hardware and power consumption.