一种非同步时序电路的测试生成方案

Test Generation for Non-Synchronous Sequential Circuit

分析了非同步时序电路测试生成所面临的问题。根据测试状态下非同步时序电路的时序特点,结合同步时序电路测试生成算法,提出和论证了一种解决非同步时序电路测试生成问题的方案,通过为时序元件建立完全模型,将时序电路中的时钟信号引入,为非同步时序电路构建出用于测试的单时钟同步电路模型,从而直接用同步时序电路测试生成算法解决非同步电路的测试生成问题。

The problem of test generation for sequential circuits belongs to the class of NP-complete problem. Due to its complexity test generation for sequential circuits always focuses on the single-clock circuits. However there are many non-synchronous circuits with multiple clocks or internal clock structures in the industrial applications, which could not be handled as the traditional synchronous circuits. In this paper, an orbicular model is presented which introduce the clock signal to the circuit model for test generation. Then a test generation flow for non-synchronous circuits is built up. By this approach, the non-synchronous circuits can be represented in synchronous models in order to utilize the synchronous sequential test generation directly.